Shared memory multi video channel display apparatus and methods

ABSTRACT

The invention includes a system and the associated method for decoding multiple video signals. The video signals may be component video, composite video or s-video signals each having multiple portions using a multimode video decoder. A selection stage may combine the multiple video signals and select some of their video signal portions for processing. The selection stage may time-multiplex some of the video signal portions. An analog to digital conversion stage may be shared by the time-multiplexing of the video signals. A decoder stage may decode the various signal portions and provide decoded output video signals. These feature may reduce the overall cost of the system. Various clock signals may be used to operate various stages of a multimode video decoder. Some of the clock signals may run at different frequencies and others may operate at a different phase.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.11/736,542, filed Apr. 17,2007 (currently pending), which claims thebenefit of U.S. Provisional Applications Nos. 60/793,288, filed Apr. 18,2006, 60/793,276, filed Apr. 18, 2006, 60/793,277, filed Apr. 18, 2006,and 60/793,275, filed Apr. 18, 2006 each disclosure of which is herebyincorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

Traditionally, multi video channel television display screens areequipped with dual channel video processing chips which enable a user toview one or more channels simultaneously on various portions of thedisplay screen. This form of displaying a picture within a picture iscommonly referred to as picture-in-picture or PIP. FIG. 1A is an exampleof displaying two channels on various portions of the display screenhaving an aspect ratio of 4:3. A screen 100A displays a first channel112 on the majority portion of the screen simultaneously with a secondchannel 122 that is displayed on a substantially smaller portion of thescreen. FIG. 1B is an example of a display having a first channel and asecond channel with substantially the same aspect ratio on differentportions of the screen and will be described in more detail below.

A typical television system for generating PIP display 100A is shown inFIG. 2. Television display system 200 includes, television broadcastsignals 202, a hybrid TV tuner 210, baseband inputs 280, a demodulator220, an MPEG Codec 230, an off-chip storage 240, an off-chip memory 300,video processor 250, and an external component 270 (e.g., a display).Hybrid TV tuner 210 can tune to one or more television channels providedby television broadcast signals 202. Hybrid TV tuner 210 may providedigital television signals to demodulator 220 and analog video signalcomponents (e.g., Composite Video Baseband Signals (CVBS)) to videoprocessor 250. Additionally, baseband inputs 280 may receive varioustelevision signals (e.g., CVBS, S-Video, Component, etc.) and providethem to video processor 250. Other external digital or analog signals(e.g., DVI or High Definition (HD)) may also be provided to videoprocessor 250.

The video is demodulated by demodulator 220 and is then decompressed byMPEG Codec 230. Some operations required by MPEG Codec 230 may useoff-chip storage 240 to store data. The digital signal(s) are thenprocessed by video processor 250, which can be a dual channel processingchip, in order to generate the proper signals 260 for display onexternal component 270. Video processor 250 may use off-chip memory 300to perform memory intensive video processing operations such as noisereducing and de-interlacing; 3D YC separation and frame rate conversion(FRC).

In these PIP applications, it is generally perceived that first channel112 is more important than second channel 122. Typical dual channelprocessing chips that are used to generate PIP place more qualityemphasis on the first channel video pipe, which generates the largedisplay of first channel 112. The second channel video pipe, whichgenerates the smaller display of second channel 122 is of lesser qualityin order to reduce costs. For example, 3-D video processing operations,such as de-interlacing, noise reduction, and video decoding, may beimplemented on the first channel video pipe while implementing only 2-Dvideo processing operations on the second channel video pipe. 3-D videoprocessing operations refer to operations that process video in thespatial and temporal domains, often buffering one or more frames ofvideo used in the processing operations. In contrast, 2-D videoprocessing operations only process video in the spatial domains,operating only on the current frame of video.

With the advent of wide display screens having an aspect ratio of 16:9,displaying two channels having the same size or an aspect ratio of 4:3on the same screen has become increasingly higher in demand. This formof application is commonly referred to as picture-and-picture (PAP). InFIG. 1B screen 100B displays a first channel 110 and a second channel120 having substantially the same aspect ratio is displayed on a secondportion of the screen. In these applications the first channel should begenerated with similar quality as the second channel.

An implementation of 3-D video processing on both the first and secondvideo channel pipes is therefore needed to produce two high-qualityvideo images. Performing 3-D video processing to produce the desireddisplay generally requires memory intensive operations that have to beperformed within a time frame suitable to display the images withoutloss in quality or integrity. The memory operations increaseproportionally with the number of channels that require 3-D videoprocessing. Typical dual video processing chips lack ability to processtwo video signals with high-quality and are therefore becoming obsoletewith the increase in demand to display two channels having high videoquality.

One reason that typical dual video processing chips lack in the abilityto process multiple high-quality video signals, is the large amount ofdata bandwidth required between the video processor and the off-chipmemory. Traditionally, a portion of the video processing chip pipelineincludes a noise reducer and de-interlacer each requiring high databandwidth with the off-chip memory.

In particular, the noise reducer works primarily by comparing one fieldto the next field and removing portions of the field that are not thesame in each field. For this reason, the noise reducer requires storageof at least two fields for comparison with a current field. Thede-interlacer reads the two fields that were stored and combines them,thereby reversing the operations of the interlacer.

FIG. 3 illustrates the off-chip memory access operations of the noisereducer and de-interlacer of a typical video processor. A portion of thevideo processing pipeline includes a noise reducer 330, a de-interlacer340, and off-chip memory 300, which contains at least four field buffersections 310, 311, 312, and 313.

During a first field interval, noise reducer 330 reads a field buffersection 310 compares it to a video signal 320, produces a new field withreduced noise and writes this field output 322 to two field buffersections 311 and 312. The contents that were previously stored in fieldbuffer sections 311 and 312 are copied over to field buffer sections 310and 313, respectively. Thus, at the end of the field interval, fieldoutput 322 of noise reducer 330 is stored in field buffer sections 311and 312 and the fields previously stored in field buffer sections 311and 312 are now in field buffer sections 310 and 313, respectively.

During the following field interval, field buffer section 312 containingthe field output from noise reducer 330 from the previous field intervalis read by de-interlacer 340, field buffer section 313 containing thefield output from noise reducer 330 from the field interval previous tothis field interval that was stored in field buffer section 312 is readby de-interlacer 340. Field output 322 of noise reducer 330 of thecurrent field interval is also read by de-interlacer 340. De-interlacer340 processes these field segments and combines them to provide ade-interlaced output 342 to the next module in the video pipeline.

The exemplary aforementioned video pipeline portions perform theseoperations for a single channel and its operations would be multipliedfor each additional channel. Therefore, since memory access bandwidthincreases proportionally with the amount of data that has to bewritten/read in the same interval, performing noise reduction andde-interlacing on multiple channels would increase the data bandwidth inthe same manner. The incredible bandwidth demand of the above videoprocessing operations limit the ability to perform these operationssimultaneously.

Therefore, it would be desirable to have systems and methods forreducing memory access bandwidth in various sections of one or morevideo pipeline stages of one or more channels in order to produce adisplay having multiple high-quality video channel streams.

SUMMARY OF THE INVENTION

In accordance with the principles of the present invention systems andmethods are provided for reducing memory access bandwidth in varioussections of one or more video pipeline stages of one or more channels inorder to produce a display having multiple high quality video channelstreams.

A plurality of video input signals may be decoded, where at least one ofthe plurality of video input signals includes two or more video inputsignal portions. The plurality of video input signals may be received.At least three video input signal portions may selectively be combinedto provide two selected video signals. An analog to digital conversionmay be performed to process the selected video signals. The processedvideo signals may be decoded to produce at least one decoded videosignal.

In accordance with the principles of the present invention, methods andapparatus are provided for reducing memory access bandwidth in varioussections of one or more video pipeline stages of one or more channels inorder to produce a display having multiple high-quality video channelstreams. A dual video processor may receive one or more analog ordigital signals which may be in different formats. A dual video decoder(e.g., NTSC/PAL/SECAM video decoder) capable of decoding twosimultaneous video signals in one or more video modes may be provided.In one of the video modes, the dual video decoder may perform timemultiplexing to share at least one component such as an analog todigital converter, used in decoding the video signals.

The outputs of the video decoder, or another set of video signalsprovided by another component in the system, may be provided to signalprocessing circuitry (e.g., a noise reducer and/or a de-interlacer). Thesignal processing circuitry may access a memory device to store variousfield lines. Some of the stored field lines, that may be needed by thesignal processing circuitry, may be shared. The sharing of some storedfield lines reduces overall memory bandwidth and capacity requirements.The signal processing circuitry may be capable of performing multiplefield line processing. A set of field line buffers may be provided tostore field lines for multiple field segments and may provide the datato the corresponding inputs of the signal processing circuitry. Tofurther reduce storage, some of the field line buffers may also beshared among the signal processing circuitry.

The outputs of the video decoder, or another set of video signalsprovided by another component in the system, may be provided to one ormore scalers for producing differently scaled video signals. The scalermay be configured to be placed in various slots before the memory, afterthe memory, or if no memory access is desired either before or after(i.e., between the memory). If a video signal is to be up-scaled, thescaler may be placed after the memory in order to reduce the amount ofdata that is stored to the memory. If a video signal is to bedownscaled, the scaler may be placed before the memory in order toreduce the amount of data that is stored to the memory. Alternatively,one scaler may be configured to be placed before the memory whileanother scaler may be configured to be placed after the memory therebyproviding two video signals that are scaled differently (i.e., one maybe up-scaled while the other may be downscaled) while reducing theamount of memory storage and bandwidth.

The outputs of the video decoder, or another set of video signalsprovided by another component in the system, may be provided to one ormore frame rate conversion units. A blank time optimizer (BTO) mayreceive data pertaining to a field line of a frame of a video signal ata first clock rate. The BTO may determine the maximum amount of timeavailable before the next field line of the frame is received. Based onthis determination the BTO may send or receive the field line of theframe to memory at a second clock rate. The second clock rate used forthe memory access may be substantially slower than the first, therebyreducing memory bandwidth and enabling another video signal that mayhave a shorter amount of available time between field lines to accessmemory faster. In turn, the BTO essentially distributes memory accessfrom several memory clients (i.e., units requiring memory access) in away that promotes efficient use of the memory bandwidth.

The video signal outputs of the BTO or another set of video signalsprovided by another component in the system, may be provided to anoverlay engine for further processing. In the overlay engine, two ormore video signals may be overlaid and provided to a color managementunit (CMU). The CMU may receive the overlaid video signal and mayprocess the overlaid video signal in portions. Upon receiving anindication that a portion of the overlaid video signal corresponds to afirst video signal, the CMU may process the video signal portion usingparameters that correspond to the first video signal portion and providean output. Alternatively, upon receiving an indication that a portion ofthe overlaid video signal corresponds to a second video signal, the CMUmay process the video signal portion using parameters that correspond tothe second video signal portion and provide an output. A multi-plane(M-plane) overlay circuit in the overlay engine may receive two or morevideo signals, where one of these signals may be provided by the CMU,and provide an overlaid signal. The video signals may include a prioritydesignator, and the overlay circuitry may then overlay the signals basedon the priority designator.

The output of the overlay engine or another set of video signalsprovided by another component in the system which may be progressive,may be provided to a primary and/or auxiliary output stage.Alternatively, video signals may bypass the overlay engine and beprovided to a primary and/or auxiliary output stage. In the primaryand/or auxiliary output stages the video signals may undergo formatconversion or processing to meet the requirements of a primary and/orauxiliary device such as, for example a display device and a recordingdevice.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the invention will beapparent upon consideration of the following detailed description, takenin conjunction with the accompanying drawings, in which like referencecharacters refer to like parts throughout, and in which:

FIGS. 1A and 1B is exemplary illustration of two channels beingdisplayed on various portions of the same screen;

FIG. 2 is an illustration of generating PIP display;

FIG. 3 is an illustration of off-chip memory access operations of anoise reducer and a de-interlacer in a typical video processor;

FIG. 4 is an illustration of a television display system in accordancewith principles of the present invention;

FIG. 5 is a detailed illustration of the functions of an onboard videoprocessing section of a dual video processor in accordance withprinciples of the present invention;

FIG. 6 is an illustration of a clock generation system in accordancewith principles of the present invention;

FIGS. 7-9 are illustrations of three modes of generating video signalsin accordance with principles of the present invention;

FIG. 10 is an illustration of an exemplary implementation of using twodecoders to generate three video signals in accordance with principlesof the present invention;

FIG. 11 is an exemplary timing diagram for time division multiplexingtwo portions of two video signals in accordance with principles of thepresent invention;

FIG. 12 is a detailed illustration of the functions of the front endvideo pipeline of the dual video processor in accordance with principlesof the present invention;

FIG. 13 is an illustration of off-chip memory access operations of anoise reducer and a de-interlacer in accordance with principles of thepresent invention;

FIG. 14 is an exemplary illustrative timing diagram of the off-chipmemory access operations of a noise reducer and a de-interlacer inaccordance with principles of the present invention;

FIG. 15 is an illustration of multiple field line processing inaccordance with principles of the present invention;

FIG. 16 is a detailed illustration of performing frame rate conversionand scaling in accordance with principles of the present invention;

FIG. 17 is an illustration of a scaler positioning module in accordancewith principles of the present invention;

FIG. 18 is an illustrative example of the operation of a BTO multiplexorin accordance with principles of the present invention;

FIG. 19 is a detailed illustration of the color processing and channelblending (CPCB) video pipeline of the dual video processor in accordancewith principles of the present invention;

FIG. 20 is a detailed illustration of the overlay engine in accordancewith principles of the present invention;

FIG. 21 is a detailed illustration of the color management unit inaccordance with principles of the present invention; and

FIG. 22 is a detailed illustration of the back end video pipeline of thedual video processor in accordance with principles of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The invention relates to methods and apparatus for reducing memoryaccess bandwidth and sharing memory and other processing resources invarious sections of multiple video pipeline stages of one or morechannels in order to produce one or more high-quality output signals.

FIG. 4 illustrates a television display system in accordance with theprinciples of the present invention. The television display systemdepicted in FIG. 4 may include, television broadcast signals 202, a dualtuner 410, MPEG Codec 230, off-chip storage 240, off-chip memory 300, adual video processor 400, a memory interface 530 and at least oneexternal component 270. Dual tuner 410 may receive television broadcastsignals 202 and produce a first video signal 412 and a second videosignal 414. Video signals 412 and 414 may then be provided to a dualdecoder 420. Dual decoder 420 is shown to be internal to dual videoprocessor 400, but may alternatively be external to video processor 400.Dual decoder 420 may perform similar functions as decoder 220 (FIG. 2)on first and second video signals 412 and 414. Dual decoder 420 mayinclude at least a multiplexor 424 and two decoders 422. In alternativearrangements, multiplexor 424 and one or two of decoders 422 may beexternal to dual decoder 420. Decoders 422 provide decoded video signaloutputs 426 and 428. It should be understood that decoders 422 may beany NTSC/PAL/SECAM decoders different from MPEG decoders. The inputs todecoders 422 may be digital CVBS, S-Video or Component video signals andthe output of decoders 422 may be digital standard definition such asY-Cb-Cr data signals. A more detailed discussion of the operation ofdual decoder 420 is provided in connection with FIGS. 7, 8, 9, and 10.

Multiplexor 424 may be used to select at least one of two video signals412 and 414 or any number of input video signals. The at least oneselected video signal 425 is then provided to decoder 422. The at leastone selected video signal 425 appears in the figure as a single videosignal to avoid overcrowding the drawing, however, it should beunderstood the video signal 425 may represent any number of videosignals that may be provided to the inputs of any number of decoders422. For example, multiplexor 424 may receive 5 input video signals andmay provide two of the 5 input video signals to two different decoders422.

The particular video signal processing arrangement shown in FIG. 4 mayenable the internal dual decoder 420 on dual video processor 400 to beused thereby reducing the cost of using an external decoder which may berequired in the time-shifting applications. For example, one of theoutputs 426 and 428 of dual decoder 420 may be provided to a 656 encoder440 to properly encode the video signal to standard format prior tointerlacing the video signals. 656 encoder 440 may be used to reduce thedata size for processing at a faster clock frequency. For example, insome embodiments, 656 encoder 440 may reduce 16-bits of data, h-sync andv-sync signals to 8-bits for processing at double the frequency. Thismay be the standard to interface between SD video and any NTSC/PAL/SECAMdecoders and MPEG encoders. The encoded video signal 413 may then beprovided to an external MPEG Codec 230, for example, via a port on thevideo processor, to generate a time shifted video signal. Another port,flexiport 450 on dual video processor 400 may be used to receive thetime shifted video signal from MPEG Codec 230. This may be desirable toreduce the complexity of the video processor by processing portions ofdigital video signals outside of the video processor. Moreover,time-shifting performed by MPEG Codec 230 may require operations thatinclude compression, decompression and interfacing with non-volatilemass storage devices all of which may be beyond the scope of the videoprocessor.

Other video signals such as a cursor, an on-screen display, or variousother forms of displays other than broadcast video signals 202 that maybe used in at least one external component 270 or otherwise provided toan external component, may also be generated using dual video processor400. For example, dual video processor 400 may include a graphics port460 or pattern generator 470 for this purpose.

The decoded video signals, as well as various other video signals,graphics generator 460, or pattern generator 470, may be provided toselector 480. Selector 480 selects at least one of these video signalsand provides the selected signal to onboard video processing section490. Video signals 482 and 484 are two illustrative signals that may beprovided by selector 480 to onboard video processing section 490.

Onboard video processing section 490 may perform any suitable videoprocessing functions, such as de-interlacing, scaling, frame rateconversion, and channel blending and color management. Any processingresource in dual video processor 400 may send data to and receive datafrom off-chip memory 300 (which may be SDRAM, RAMBUS, or any other typeof volatile storage) via memory interface 530. Each of these functionwill be described in more detail in connection with the description ofFIG. 5.

Finally, dual video processor 400 outputs one or more video outputsignals 492. Video output signals 492 may be provided to one or moreexternal components 270 for display, storage, further processing, or anyother suitable use. For example, one video output signal 492 may be aprimary output signal that supports high-definition TV (HDTV)resolutions, while a second video output signal 492 may be auxiliaryoutput that supports standard definition TV (SDTV) resolutions. Theprimary output signal may be used to drive a high-end external component270, such as a digital TV or a projector at the same time as theauxiliary output is used for a standard definition (DVD) video recorder,a standard-definition TV (SDTV), a standard-definition preview display,or any other suitable video application. In this way, the auxiliaryoutput signal may enable a user to record an HDTV program on anysuitable SDTV medium (e.g., a DVD) while allowing the user tosimultaneously view the program on an HDTV display.

FIG. 5 illustrates the functions of onboard video processing section 490of dual video processor 400 in greater detail. Onboard video processingsection 490 may include an input signal configuration 510, a memoryinterface 530, a configuration interface 520, a front end pipelinesection 540, a frame rate conversion (FRC) and scaling pipeline section550, a color processing and channel blending pipeline section 560, and abackend pipeline section 570.

Configuration interface 520 may receive control information 522 from anexternal component such as a processor via, for example an I2Cinterface. Configuration interface 522 may be used to configure inputsignal configuration 510, front end 540, frame rate conversion 550,color processor 560, backend 570, and memory interface 530. Input signalconfiguration 510 may be coupled to external inputs on dual videoprocessor 400 in order to receive video signals on input 502 (such asHDTV signals, SDTV signals, or any other suitable digital video signals)and selected video signals 482 and 484 (FIG. 4). Input signalconfiguration 510 may then be configured to provide at least one of thereceived video signals (e.g., signals 482, 484 and 502) as video sourcestreams 512 to front end 540.

Based on this configuration, various ones of these inputs provided toonboard video processing section 490 may be processed at different timesusing the onboard video processing pipeline. For example, in oneembodiment dual video processor 400 may include eight input ports.Exemplary ports may include two 16-bit HDTV signal ports, one 20-bitHDTV signal port, three 8-bit SDTV video signal ports which may be inCCIR656 format, one 24-bit graphics port and one 16-bit externalon-screen display port.

Front end 540 may be configured to select between at least one videosignal streams 512 (i.e., channels) of the available inputs and processthe selected video signal stream(s) along one or more video processingpipeline stages. Front end 540 may provide processed video signalstream(s) from one or more pipeline stages to frame rate conversion andscaling pipeline stage 550. In some embodiments, front end 540 mayinclude three video processing pipeline stages and provide threeseparate outputs to FRC and scaling pipeline stage 550. In FRC andscaling pipeline stage 550 there may be one or more processing channels.For example, a first channel may include a main scaler and frame rateconversion unit, a second channel may include another scaler and framerate conversion unit, and a third channel may include a lower costscaler. The scalars may be independent of each other. For example, onescalar may upsize the input image while another may downsize the image.Both scalars may be capable of working with 444 pixels (RGB/YUB 24-bits)or 422 pixels (YC 16-bits).

Color processing and channel blending pipeline stage 560 may beconfigured to provide color management functions. These functions mayinclude color re-mapping, brightness, contrast, hue & saturationenhancement, gamma correction and pixel validation. Additionally, colorprocessing and channel blending pipeline stage 560 may provide videoblending functions, overlaying different channels, or blend or overlaytwo blended video channels with a third channel.

Back end pipeline stage 570 may be configured to perform dataformatting, signed/unsigned number conversion, saturation logic, clockdelay, or any other suitable final signal operations that may be neededprior to the output of one or more channels from dual video processor400.

Each of the various pipeline stage segments may be configured to senddata to and receive data from off-chip memory 300 using memory interface530. Memory interface 530 may include at least a memory controller and amemory interface. The memory controller may be configured to run at amaximum speed supported by the memory. In one embodiment, the data busmight be 32-bits and may operate at a frequency of 200 MHz. This bus mayprovide a throughput substantially close to 12.8 gigabits per second.Each functional block that uses memory interface 530 (i.e., memoryclient) may address the memory in a burst mode of operation. Arbitrationbetween various memory clients may be done in a round robin fashion orany other suitable arbitration scheme. A more detailed discussion of thevarious pipeline segments is provided in connection with the descriptionof FIGS. 12, 19, 20, 21 and 22.

Various components and pipeline stages in dual video processor 400 mayrequire a different clocking mechanisms or clock frequencies. FIG. 6illustrates a clock generation system 600 that generates a variety ofclock signals for this purpose. Clock generation system 600 includes atleast a crystal oscillator 610, generic analog phase-locked loopcircuitry 620, digital phase locked loop circuitries 640 a-n and memoryanalog phase-locked loop circuitry 630. The output 612 of crystaloscillator 610 may be coupled to generic phase locked loop 620, memoryphase-locked loop 630, another component in dual video processor 400, orany suitable component external to the processor as needed.

Memory analog phase-locked loop circuitry 630 may be used to generate amemory clock signal 632 and additionally other clock signals ofdifferent frequencies 636 which may be selected by selector 650 for useas a clock signal 652 to operate a memory device (e.g., 200 MHz DDRmemory) or another system component.

Generic analog phase-locked loop 620 may generate a 200 MHz clock thatmay be used as a base clock for one or more digital phase-locked loop(PLL) circuitries 640 a-n. Digital PLL circuitry 640 a-n may be used inopen loop mode, where it behaves as a frequency synthesizer (i.e.,multiplying the base clock frequency by a rational number).Alternatively, digital PLL circuitry 640 a-n may be used in closed loopmode, where it may achieve frequency lock by locking onto a respectiveinput clock signal 642 a-n (e.g., a video sync input). The digital PLLhas the ability, in closed loop mode, to achieve accurate frequency lockto very slow clock signals. For example, in the realm of videoprocessing the vertical video clock signal (e.g., v-sync) may be in therange of 50 to 60 Hz. Various system components may use outputs 644 a-nof digital PLL circuitry 640 a-n for different operations that mayrequire a variety of open loop or closed loop signals. Each of outputs640 a-n should be understood to be capable of providing clock signals ofdifferent frequencies or the same frequencies.

For example, one component that may use clock signals generated bydigital PLL circuitry 640 a-n is dual decoder 420 (FIG. 4), theoperation of which is described in more detail in connection with FIGS.7, 8, 9, and 10. Dual decoder 420 may include the decoders 422 (FIG. 4).Decoders 422 may be used in various modes of operation as described inconnection with FIGS. 7, 8, and 9.

FIGS. 7, 8, and 9 illustrate three exemplary modes of operation usingdecoders 422 to generate video signals 426 and 428. These three modes ofoperation may provide for example, composite video signals, s-videosignals, and component video signals.

A first of these three modes, which may be used to generate compositevideo signals, is shown in connection with FIG. 7. The first decodermode may include a DC restore unit 720, an analog to digital converter730, and decoder 422 each of which may be included in dual decoded 420(FIG. 4). Video signal 425 (FIG. 4), which may be provided by dual tuner410 or in an alternative arrangement by multiplexor 424, is provided toDC restore unit 720. DC restore unit 720 may be used when video signal425, which may be an AC coupled signal, has lost its DC reference andshould have it periodically reset in order to retain videocharacteristic information such as brightness. The video signal from DCrestore unit 720 is digitized by analog to digital converter 730 andprovided to decoder 422.

In the first mode, decoder 422 may use the digitized video signal 732from a single analog to digital converter to generate a composite videosignal. Analog to digital converter 730 and decoder 422 may operate byreceiving digital clock signals 644 a-n (FIG. 6)—which may be, forexample, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30 MHz.Additionally, decoder 422 may control the operation of DC restore unit720 using an output feedback signal 427. Output feedback signal 427 maybe, for example, a 2-bit control signal that instructs DC restore unit720 to increase or decrease the DC output on the video signal providedto analog to digital converter 730.

A second of the three modes, which may be used to generate s-videosignals, is shown connection with FIG. 8. The second decoder mode mayinclude all of the elements described in the first mode in addition to asecond analog to digital converter 820. Video signal 425 (FIG. 4) may besplit into a first portion 812 and a second portion 810. First portion812 of the signals of video signal 425 (FIG. 4), which may be providedby multiplexor 424, may be provided to DC restore unit 720 and a secondportion 810 of the signals of video signal 425 (FIG. 4) may be inputtedto second digital to analog converter 820. First portion 812 of videosignal 425 from DC restore unit 720 is digitized by second analog todigital converter 730 and provided to decoder 422. Additionally, secondportion 810 of video signal 425 is also provided to decoder 422 byanalog to digital converter 820. S-Video signals require a two wireanalog port for connecting to various devices (e.g., VCR, DVD player,etc.).

In this second mode, decoder 422 may use the digitized video signals 732and 832 from two analog to digital converters 730 and 820 to generate ans-video signal. Analog to digital converters 730 and 820 and decoder 422may operate by receiving digital clock signals 644 a-n (FIG. 6)—whichmay be, for example, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, or 30 MHz.In some embodiments, first portion 812 of the video signal may be theY-channel of video signal 425 and the second portion 810 of video signal425 may be the chroma channel of the video signal.

A third of the three modes, which may be used to generate componentvideo signals, is shown in connection with FIG. 9. The third decodermode may include all the elements described in the second mode inaddition to a second and third DC restore unit, 930 and 920, and amultiplexor 940. Video signal 425 may be split into a first portion 914,a second portion 910, and a third portion 912. First portion 914 of thevideo signal 425 (FIG. 4), which may be provided by multiplexor 424, maybe provided to DC restore unit 720, second portion 910 of the signals ofvideo signal 425 (FIG. 4) may be provided to DC restore unit 930, andthird portion 912 of the signals of video signal 425 (FIG. 4) may beprovided to DC restore unit 920. Component video signals require a threewire analog port for connecting to various devices (e.g., VCR, DVDplayer, etc.).

First portion 914 of video signal 425 from DC restore unit 720 isdigitized by analog to digital converter 730 and provided to decoder422. Second and third portions 910 and 912 of video signals 425 from DCrestore units 930 and 920 are selectively digitized (e.g., by beingselected using multiplexor 940) by analog to digital converter 820 andprovided to decoder 422. Multiplexor 940 may receive control signals 429from decoder 422 in order to time multiplex second and third portions910 and 912 of video signal 425 through analog to digital converter 820.

In the third mode, in some embodiments, decoder 422 may use thedigitized video signals 732 and 832 from the two analog to digitalconverters 730, 820 to generate a component video signal. Analog todigital converters 730 and 820 and decoder 422 may operate by receivingdigital clock signals 644 a-n (FIG. 6)—which may be, for example, 20,21, 22, 23, 24, 25, 26, 27, 28, 29, or 30 MHz. Additionally, decoder 422may control the operation of DC restore units 720, 930, and 920 using anoutput feedback signal 427. In some embodiments, first, second and thirdportions 914, 910 and 912 of video signal 425 may be the Y-channel,U-channel and V-channel, respectively, of video signal 425.

It should be understood that various commonly available types of DCrestore units, digital to analog converters and video decoders may beused to perform the aforementioned functions and for the sake ofbrevity, their particular operations are being omitted from thisdiscussion.

In one embodiment show in FIG. 10, all three decoder modes may beimplemented using two of decoders 422 and three of analog to digitalconverters 730 or 820. The arrangement described in FIG. 10 may enabledual decoder 420 (FIG. 4) to provide at least two video signals 426 and428 (i.e., one video signal from each decoder) substantiallysimultaneously that may correspond to any two of the three modes.

FIG. 10 illustrates an exemplary implementation of using two decoders togenerate either two composite video signals, one composite and ones-video signals, one composite and one component video signals, or twos-video signals. The exemplary implementation shown in FIG. 10 includes,a set of multiplexors 1020, 1022, 1023, 1025, 1021, 1024, 1026, 1027,and 1028; three analog to digital converters 730, 820, 1010; four DCrestore units 720, 721, 930, 920; a demultiplexor 1040; and two decoders422 a and 422 b.

The exemplary implementation of FIG. 10, when used to generate twocomposite video signals, may operate in the following manner. A firstvideo signal 425 a may be coupled to the first input of multiplexor 1020and a second video signal 914 may be coupled to the second input ofmultiplexor 1024. The first input of multiplexor 1020 may be selectedand output to the fourth input of multiplexor 1021 to be input to DCrestore unit 720. The second input of multiplexor 1024 may be selectedand output to DC restore unit 721. The operations of the remainingportions of the implementation are similar to that which was describedin connection with FIG. 7 in which a composite video signal isgenerated. For example, DC restore units 720 and 721, analog to digitalconverters 730 and 1010, and decoders 422 a and 422 b operate in asimilar manner to generate the composite video signals as described inFIG. 7.

The generation of one composite and one s-video signals or one compositeand one component video signals using the exemplary implementation shownin FIG. 10 is performed in a similar manner as the generation of twocomposite video signals described above. For example, first and secondvideo signal portions 812 and 810 of video signal 425 used forgenerating s-video signals are provided to multiplexors 1022 and 1026.The outputs of multiplexors 1022 and 1026 are provided to multiplexors1021 and 1027 which select the video signals that are to be processed byanalog to digital converters 730 and 820. Similarly, multiplexor 1024selects which video signals are to be processed by analog to digitalconverter 1010. A more detailed description of the multiplexor inputselections for the various modes of operation are depicted in Table 1shown below.

The exemplary implementation shown in FIG. 10 also enables thegeneration of two s-video signals 426 and 428. To provide thisfunctionality, a first clock signal 644 a operating at a first frequencyand a first phase (e.g., 20 MHz) is provided to analog to digitalconverter 730 and to decoder 422 a. A second clock signal 644 boperating at a second frequency that may be 180 degrees out of phasefrom the first clock signal (e.g., 20 MHz at 180 degree out of phase)may be provided to analog to digital converter 1010 and to decoder 422b. A third clock signal 644 c at a third frequency that is substantiallydouble the frequency of the first clock signal and having the same phaseas the first clock signal (e.g., 40 MHz) may be provided to analog todigital converter 820. Clock signal 644 b is provided to multiplexor1030 to selectively couple clock signal 644 b to multiplexors 1026 and1027. By coupling the clock signals to the select inputs of multiplexors1026 and 1027 it is possible to perform time-division multiplexing onvideo signal inputs 810 a-c on analog to digital converter 820. Clocksignal 644 a is coupled to demultiplexor 1040 to demultiplex the timedivided video signal. A more clear description of the time-divisionmultiplexing operations is provided in connection with FIG. 11.

FIG. 11 illustrates an exemplary timing diagram for time-divisionmultiplexing two second portions 810 of two video signals 425. By timedivision multiplexing the operations, the need for a fourth analog todigital converter may be obviated thereby reducing the total cost ofdual video processor 400. The timing diagram shown in FIG. 11 includes,three clock signals that correspond to the first, second and third clocksignals 644 a, 644 b and 644 c respectively, and outputs of three analogto digital converters 730, 1010, and 820. As shown in the diagram clock1 and clock 2 operate at half of the frequency of clock 3 and changewith the falling edge of clock 3.

As shown, between the time period of T1 and T4, a full period of clock644 a (clock 1) completes and the output of analog to digital converter730 (ADC 1) corresponding to the first portion 812 a-c of a first videosignal (S0) is available for processing by decoder 422 a. On the risingedge of clock 3 at the beginning of time period T2, analog to digitalconverter 820 (ADC 3) begins processing a second portion 810 a-c of asecond video signal (S1) and completes processing at the end of timeperiod T3.

At the beginning of time period T3, analog to digital converter 820 (ADC2) begins processing a first portion 810 a-c of video signal S1 andcompletes at the end of time period T6. The output of ADC 2corresponding to the first portion 810 a-c of video signal S1 becomesavailable for processing by decoder 422 b at the end of time period T6.On the rising edge of clock 3 at the beginning of time period T4, analogto digital converter 820 (ADC 3) begins processing a second portion 810a-c of video signal S0 and completes processing at the end of timeperiod T5.

Thus, at the end of time period T6, two portions of two video signals S0and S1 have completed processing using only three analog to digitalconverters.

On the rising edge of clock 3 between the time periods T5 and T6,demultiplexor 1040 provides the output of second portion 810 a-c ofvideo signal S0 from ADC 3 to decoder 644 a for producing processedvideo signal 426. At the same time second portion 812 of video signal S1is selected for processing by analog to digital converter 820 (ADC 3)and becomes available at the end of time period T7.

The foregoing demonstrates one embodiment for producing two s-videosignals 426 and 428 using three analog to digital converters 730, 1010,and 820. Table 1 below summarizes the various exemplary select signalsthat may be provided to the corresponding multiplexors for producingvarious combinations of composite (cst), component (cmp) and s-videosignals (svid).

TABLE 1 Video1 Video2 M0_sel M1_sel M2_sel M3_sel M4_sel M5_sel M6_selM7_sel 425a (cst) 425e (cst) 0, 0 X, X 1, 1 X, X X, X 0, 1 X, X X, X425a (cst) 910, 912, 914 0, 0 X, X 1, 1 X, X X, X 1, 0 X, X 1, 429 (cmp)425b (cst) 812a, 810a 0, 1 X, X 1, 1 X, X 0, 0 0, 0 0, 0 0, 0 (svid)812a, 810a 812b, 810b X, X 0, 0 0, 0 X, X 0, 1 0, 0 0, 644b 0, 0 (svid)(svid) 812a, 810a 812c, 810c X, X 0, 0 0, 0 X, X 1, 0 0, 0 644b, 0 0, 0(svid) (svid) 812b, 810b 812c, 810c X, X 0, 1 0, 0 X, X 1, 0 0, 0 644b,1 0, 0 (svid) (svid)

Dual decoder 420 may also be configured to handle unstable analog ordigital signals which may be received from a video cassette recorder(VCR). Unstable signals may be produced by a VCR due to various modes ofoperation such as fast forwarding, fast rewinding or pausing modes. Dualdecoder 420 may be able to process these types of signals to provide agood quality output signal during such situations.

Unstable video signals may be caused by un-stable sync signals generatedby the VCR. One suitable technique for processing unstable sync signalsmay be to buffer the unstable video signal. For example afirst-in-first-out (FIFO) buffer may be placed near the output of thedecoder. First, the decoder output data may be written to the FIFObuffer using unstable sync signals as the reference. The sync signalsand the clock may be re-generated or re-created from a logic blockwithin the decoder and may then be used for reading the data from theFIFO buffer when such modes of operation are encountered. Thus, theunstable video signal may be output with a stable sync signal. In allother scenarios or modes of operation, the FIFO buffer may be bypassedand the output may be the same as the FIFO's input.

Alternatively, implementing FIFO buffers in the off-chip memory mayenable the proper processing of unstable sync signals. For example, whenan unstable sync signal is detected, the decoder may be placed in 2-Dmode thereby using less off-chip memory. A substantial portion ofoff-chip memory 300, which is normally used for 3-D operations, becomesfree and may be used for implementing the aforementioned FIFO buffer(i.e., the equivalent of at least one full data vector is available asfree memory space). Moreover, the FIFO buffer inside the off-chip memorymay be capable of storing the pixels for a full frame, so even if thewrite and read rates are not matched, at the output the frames eitherget repeated or get dropped. The repeating or dropping of a particularframe or of fields within a frame may still enable the system to displaya reasonably good picture.

FIG. 12 illustrates in more detail the exemplary functionality of frontend 540 within the video pipeline. In particular, channel selector 1212may be configured to select four channels from multiple video sourcestreams 512. The four channels may be processed along 4 pipelined stageswithin front end 540. In some embodiments, the four channels mayinclude: a main video channel, a PIP channel, an on-screen display (OSD)channel, and a data instrumentation or testing channel.

Front end 540 may implement various video processing stages 1220 a, 1220b, 1230, and 1240 on any of the channels. In some embodiments, thevarious channels may share one or more resources from any of the otherstages to increase processing power of the various channels. Someexamples of functions that may be provided by video processing stages1220 a and 1220 b may include noise reduction and de-interlacing whichmay be used for producing maximum picture quality. The noise reductionand de-interlacing functions may also share off-chip memory 300 and, assuch the memory is denoted as shared memory stages 1260 which will bedescribed in more detail in connection with the description of FIGS. 13and 15. To avoid overcrowding the drawing, shared memory stages 1260 areshown in FIG. 12 as being part of the processing stages corresponding tochannel 1. However, it should be understood that one or more sharedmemory stages 1260 may be part of any of the channel pipelines in frontend 540.

Noise reduction may remove impulse noise, Gaussian noise (spatial andtemporal), and MPEG artifacts such as block noise and mosquito noise.De-interlacing may include generating progressive video from interlacedvideo by interpolating any missing lines using edge-adaptiveinterpolation in the presence of motion. Alternatively, de-interlacingfunctions may use a combination of temporal and spatial interpolationadaptively based on motion. Both the noise reducer and de-interlacer mayoperate in the 3-D domain and may require storing fields of frames inoff-chip memory. Hence, the de-interlacer and noise reducer may act asclients to memory interface 530 which may be used to access off-chipmemory. In some embodiments, the noise reducer and de-interlacer mayshare the off-chip memory to maximize memory space and process data inthe most efficient manner—as shown by the shared memory stages 1260.This process will be described in more detail in connection with thedescription of FIGS. 13 and 15.

Any of the three video processing stages 1220 a, 1220 b, and 1230 mayrun format conversion to convert a video signal into the desired domain.For example, this type of conversion may be used to change an inputvideo signal stream to YC 4:2:2 format in 601 or 709 color-space.

Front end 540 may also provide an instrumentation pipeline 1240 to rundata instrumentation functions. Instrumentation pipeline 1240 may beused, for example, to find the start and end pixel and line positions ofan active video or to find the preferred sampling clock phase when thereis a controllable phase sampler (ADC) upstream. Performing theseoperations may help in auto-detecting input channel parameters such asresolution, letter-boxing, and pillar-boxing. Moreover, detecting suchchannel parameters may aid in using them to control features likescaling and aspect ratio conversion through a micro-controller or anyother suitable processing element. Front end 540 may also run sync videosignal instrumentation functions on all four channels in order to detecta loss of sync signal, a loss of clock signal, or an out-of-range syncor clock signal. These functions may also be used to drive powermanagement control through a micro-controller or any other suitableprocessing element.

At the end of front end 540, a set of FIFO buffers 1250 a-c may samplethe video stream to provide sampled video signals 1252, 1254, and 1256,which may be used for retiming the selected channels, between front end540 and frame rate conversion and scaling 550 (FIG. 5) pipeline stages.

A more detailed description of shared memory stages 1260 is provided inconnection with the description of FIGS. 13 and 15. In particular, asillustrated in FIG. 13 the shared memory stages 1260 may include atleast the functions of a noise reducer 330 and a de-interlacer 340. Bothof these functions are temporal functions that may need frame storage inorder to produce a high-quality image. By enabling various memory accessblocks (i.e., memory clients) to share off-chip memory 300, the size ofoff-chip memory 300 and bandwidth required for interfacing with off-chipmemory 300 may be reduced.

Noise reducer 330 may operate on two fields of the interlaced input in3-D mode. The two fields that noise reducer 330 may operate on mayinclude live field 1262 and a field that was two fields prior to livefield 1262 (i.e., previous to the previous field 332). De-interlacer 340may operate on three interlaced fields in 3-D mode. The three fields mayinclude a live field 1262, a previous field 1330, and a previous to theprevious field 332.

As shown in FIG. 13 and FIG. 14 the field buffers 1310 and 1312 may beshared by noise reducer 330 and de-interlacer 340. Noise reducer 330 mayread from off-chip chip memory 300 a previous to the previous field 332from field buffer 1310 and process it with live field 1262 to providenoise reduced output 322. Noise reduced output 322 may be written tooff-chip memory 300 into field buffer 1312. De-interlacer 340 may readfrom off-chip chip memory 300 a previous field 1330 from field buffer1312 and previous to the previous field 332 from field buffer 1310 andprocess the read fields with either live field 1262 or noise reducedoutput 322 and provide de-interlaced video 1320 as output.

For example as illustrated in FIG. 14, live field 1262 (FIELD 1) may beprovided to noise reducer 330 for outputting noise processed output 322during a first time period (i.e., T1). After or before noise reducer 330completes processing FIELD 1 (i.e., during a time period T2), noisereduced output 322 (FIELD 1) may be provided by noise reducer 330 tode-interlacer 340 or alternatively, may bypass noise reducer 330 and beprovided directly to de-interlacer 340 via 1262 (e.g., if no noisereduction is required). In either case, during the second time period(i.e., time period T2), noise reduced output 322 (FIELD 1) may bewritten to field buffer 1312 in off-chip memory 300 by noise reducer330.

The output 1330 of field buffer 1312 (FIELD 1) may be read byde-interlacer 340 from off-chip memory 300 during the time period T2,while processing the next live field in the frame (FIELD 2). Fieldbuffer 1312 subsequently provides the noise reduced output (FIELD 1)that was processed previous to the noise processed output 322 (FIELD 2)(i.e., previous to the live field).

After or before noise reducer 330 completes processing the next field inlive field 1262 (FIELD 2) during a third time period (i.e., T3), theprevious to the live field 1330 of field buffer 1312 may be written tofield buffer 1310. The next noise reduced output 322 (FIELD 2) may bewritten to field buffer 1312 in place of the noise reduced output (FIELD1). During time period T3, the contents of field buffer 1312 is noisereduced output (FIELD 2) (i.e., previous live field) and the contents offield buffer 1310 is noise reduced output (FIELD 1) (i.e., previous toprevious the live field).

During time period T3, noise reducer 330 may operate on live field 1262(FIELD 3) and the previous to the previous live field 332 (FIELD 1).During the same time period T3, de-interlacer 340 may operate on livefield 1262 (FIELD 3) or the noise reduced output (FIELD 3), live fieldprevious to the live field 1330 (FIELD 2), and live field previous tothe previous live field 332 (FIELD 2). The sharing of off-chip memory300 between noise reducer 330 and de-interlacer 340 thereby results inusing only 2-field buffer locations whereas illustrated in FIG. 3, fourfield buffer locations are typically required in off-chip memory 300 forproviding similar functionality.

By reducing the number of field buffer locations in memory, additionalvideo processing pipelines may be provided with equal processing powerand more memory storage and bandwidth, thereby enabling the high-qualityvideo processing of at least two channels. Furthermore, the datatransfer bandwidth between dual video processor 400 and off-chip memory300 may be reduced as only a single write port and two read ports may beused to provide the aforementioned functionality.

In some other embodiments, noise reducer 330 and de-interlacer 340 mayoperate on multiple field lines in each frame simultaneously. Asillustrated in FIG. 15, each of these field lines may be stored in livefield line buffers 1520, previous live field line buffers 1530, andprevious to the previous live field line buffers 1510. Line buffers1510, 1520, and 1530 may be storage locations in dual video processor400 that may provide high efficiency and speed in storing and accessingdata. To further reduce the amount of storage space, line buffers 1510,used by both noise reducer 330 and de-interlacer 340, may be sharedamong the noise reducer and the de-interlacer modules.

As illustrated in FIG. 15, as live field 1262 is received by noisereducer 330 and de-interlacer 340, in addition to the operationdescribed in connection with FIGS. 13 and 14 for storing the live fieldin field buffer 1312, live field 1262 may also be stored in live fieldline buffers 1520. This enables noise reducer 330 and de-interlacer 340to access multiple live field lines received at different time intervalssimultaneously. Similarly, the contents stored in field buffer locations1310 and 1312 may be moved to the corresponding line buffers 1510 and1530, respectively in turn providing buffering for previous live field(noise reduced output previous to the live field) and previous to theprevious live field lines (noise reduced output previous to the previouslive field). This enables noise reducer 330 and de-interlacer 340 toaccess multiple previous live field lines and previous to the previouslive field lines simultaneously. As a result of including field linebuffers, noise reducer 330 and de-interlacer 340 may operate on multiplefield lines simultaneously. Consequently, because the noise reducer 330and de-interlacer 340 share access to the previous to the previous livefield, stored in field buffer location 1310, they may also share accessto corresponding field line buffers 1510. This in turn may reduce theamount of storage required on or substantially close to dual videoprocessor 400.

Although only three line buffers are shown in FIG. 15, it should beunderstood that any number of field line buffers may be provided. Inparticular, the number of field line buffers that are provided depend onthe amount of storage space available on dual video processor 400 and/orthe number of simultaneous field lines that may be needed by noisereducer 330 and de-interlacer 340. However, it should be understood thatany number of additional noise reduction units and de-interlacing unitsmay be provided to aid in processing multiple field lines.

For example, if two noise reducers 330 and two de-interlacers 340 thatcan each process three live field lines simultaneously are provided,then eight live field line buffers 1520, six previous live field linebuffers 1530, and six previous to the previous live field line buffers1510 may be used to process multiple field lines—where the outputs ofeach field line buffer would be coupled to the corresponding inputs ofthe noise reducers and de-interlacer units. In fact, it has beencontemplated that the contents of one or more frames can be stored inthe field buffers if the number of required noise reducers andde-interlacers and on-chip space is available.

FIG. 16 illustrates in more detail frame rate conversion and scalingpipeline 550 (FIG. 5) (FRC pipeline). FRC pipeline 550 may include atleast scaling and frame rate conversion functionality. In particular,the FRC pipeline 550 may include at least two modules used for scalingthat may be placed in two of scaler slots 1630, 1632, 1634, and 1636—onescaler for providing scaling on a first channel and one for providingscaling on a second channel. The advantages of this arrangement willbecome more apparent in the description of FIG. 17. Each of thesescaling modules in scaler slots 1630, 1632, 1634, and 1636 may becapable of performing up-scaling or down-scaling in any scaling ratio.The scalers may also include circuitry for performing aspect ratioconversion, horizontal non-linear 3 zone scaling, interlacing andde-interlacing. Scaling in some embodiments may be performed insynchronous mode (i.e., the output is synchronous with the input) orthrough off-chip memory 300 (i.e., the output may be positioned anywherewith respect to the input).

FRC pipeline 550 may also include functionality for frame rateconversion (FRC). At least two of the channels may include frame-rateconversion circuitry. In order to perform FRC, video data should bewritten to a memory buffer and read from the buffer at the desiredoutput rate. For example, an increase in frame rate results from readingthe output buffer faster than the input frame thereby causing aparticular frame to be repeated over time. A decrease in frame rateresults from reading a frame to be outputted from a buffer at a slowerrate than the particular frame is written (i.e., reading a frame slowerthan the input rate). Frame tearing or video artifacts may result fromreading a particular frame during the period in which video data isavailable (i.e., active video).

In particular, in order to avoid video artifacts such as frame tearingappearing within an active video, the repetition or dropping of framesshould happen over entire input frames and not in the middle of fieldswithin a frame. In other words, the discontinuity in video should happenonly across frame boundaries (i.e., during the vertical or horizontalsync in which no picture data is provided) and not within the region ofactive video. A tearless control mechanism 1610 may operate to alleviatediscontinuities between frames by for example, controlling when a memoryinterface 530 reads a portion of a frame in memory. FRC may be performedin normal mode or in tearless mode (i.e., using tearless controlmechanism 1610).

In addition to the two scalers that are placed in two of scaler slots1630, 1632, 1634, and 1636 in each of the first and second channels,there may be a further lower end scaler 1640 on a third channel. Thelower end scaler 1640 may be a more basic scaler, for example, a scalerthat performs only 1:1 or 1:2 up-scaling or any other necessary scalingratios. Alternatively, one of the scalers in the first and secondchannels may perform scaling on the third channel. Multiplexors 1620 and1622 may control which of the at least three channels are directed towhich of the available scalers. For example, multiplexor 1620 may selectchannel 3 for performing a first type of scaling operation in a scalerin slot 1630 or 1632 and multiplexor 1622 may select channel 1 forperforming a second type of scaling operation in a scaler in slot 1634or 1636. It should be understood that one channel may also use anynumber of available scalers.

FRC pipeline 550 also may include a smooth-movie mode in order to reducemotion jitter. For example, there may be a film-mode detection block inthe de-interlacer that detects the mode of an input video signal. If thevideo input signal is run at a first frequency (e.g., 60 Hz), it may beconverted to either a higher frequency (e.g., 72 Hz) or a lowerfrequency (e.g., 48 Hz). In the case of converting to a higherfrequency, a frame-repeat indication signal may be provided from thefilm-mode detection block to the FRC block. The frame-repeat indicationsignal may be high during a first set of the frames (e.g., one of theframes) and low during a second set of frames (e.g., four frames) ofdata that may be generated by the de-interlacer. During the portion oftime that the frame-repeat indication signal is high, the FRC may repeata frame consequently generating the correct sequence of data at thehigher frequency. Similarly, in the case of converting to a lowerfrequency, a frame-drop indication signal may be provided from thefilm-mode detection block to the FRC block. During the time period thatthe frame-drop indication signal is high a particular set of frames aredropped out of a sequence consequently generating the correct sequenceof data at the lower frequency.

Depending on the type of scaling that is desired, as shown in scalerpositioning module 1660, a scaler may be configured to be placed invarious scaler slots 1630, 1632, 1634, and 1636. Scaler slots 1632 and1636 are both located after the memory interface, although scaler slot1632 corresponds to the scaling operation performed on a first channeland scaler slot 1636 corresponds to the scaling operation performed on asecond channel. As illustrated, one scaler positioning module 1660 mayinclude a multiplexor 1624 which selects the output that corresponds toa particular scaler configuration, while another scaler positioningmodule 1660 may not include a multiplexor but instead may have theoutput of the scaler coupled directly to another video pipelinecomponent. Multiplexor 1624 provides the flexibility of implementingthree modes of operation (described in more detail in connection withFIG. 17) using only two scaler slots. For example, if multiplexor 1624is provided, a scaler positioned in slot 1630 may be coupled to thememory for providing down-scaling or up-scaling and also coupled tomultiplexor 1624. If no memory operations are desired, the multiplexor1624 may select the output of scaler slot 1630. Alternatively, if memoryoperations are required, scaler in scaler slot 1630 may scale the dataand multiplexor 1624 may select the data from another scaler whichup-scales or down-scales the data and is placed in scaler slot 1632. Theoutput of multiplexor 1624 may then be provided to another videopipeline component such as a blank time optimizer 1650 which isdescribed in more detail in connection with the description of FIG. 18.

As illustrated in FIG. 17, scaler positioning module 1660 may include atleast an input FIFO buffer 1760, a connection to memory interface 530,at least one of three scaler positioning slots 1730, 1734, and 1736, awrite FIFO buffer 1740, a read FIFO buffer 1750, and an output FIFObuffer 1770. Scaler positioning slots may correspond to the slotsdescribed in FIG. 16. For example, scaler positioning slot 1734 maycorrespond to slots 1630 or 1634, similarly scaler positioning slot 1730may correspond to slot 1630—as described above using multiplexor 1624enables slot 1630 to provide the functionality of scaler positioningslots 1730 and 1734. One or two scalers may be positioned in any one ortwo of three scaler positioning slots 1730, 1734, or 1736 with respectto memory interface 530. Scaler positioning module 1660 may be part ofany channel pipeline in FRC pipeline 550.

When synchronous mode is desired the scaler may be positioned in scalerpositioning slot 1730. In this mode, FRC may be absent from the system,obviating the need to access memory by the particular FRC channelpipeline. In this mode, the output v-sync signals may be locked to theinput v-sync signals.

The scaler may alternatively be positioned in scaler positioning slot1734. It may be desired to position the scaler in slot 1734 when FRC isneeded and the input data should be downscaled. Down-scaling the inputdata before writing to the memory (i.e., because a smaller frame sizemay be desired), consequently reduces the amount of memory storage thatmay be required. Since less data may be stored to the memory, the outputdata read rate may be reduced, thereby also reducing the total memorybandwidth that is required (and in turn reducing the cost) and providinga more efficient system.

In another scenario, the scaler may be positioned in scaler positioningslot 1736. It may be desired to position the scaler in slot 1736 whenFRC is needed and the input data should be up-scaled. The data may beprovided to the memory at a lower rate than the output data that is read(i.e., the frame size is smaller at the input than at the output). Inturn, less data may be written to the memory by storing the smallerframe and later using the scaler at the output to increase the framesize. For example, if on the other hand, the scaler was positionedbefore the memory in slot 1734 and was used to upscale the input data, alarger frame would be stored to the memory thus requiring morebandwidth. However, in this case by positioning the scaler after thememory, a smaller frame may initially be stored to the memory (thusconsuming less bandwidth) and later read back and up-scaled.

Since there may be two independent scalers in two separate scalarpositioning modules 1660, for first and second channels, if there is amemory access requirement on both of these scalar positioning modules1660, it may be the case that one of them requires high bandwidth andthe other may require a low bandwidth memory access. Blank timeoptimizer (BTO) multiplexor 1650 may provide one or more storage buffers(large enough to store one or more field lines) in order to reducememory bandwidth and enable any number of channels to share the storedfield line—thereby reducing memory storage requirements.

FIG. 18 is an illustrative example of the operation of BTO multiplexor1650 (FIG. 16). As shown in FIG. 18, a first channel (Main) occupies amajority portion of screen 1810 and a second channel (PIP) occupies asmaller portion of screen 1810. As a consequence, the PIP channel mayhave less active data and require less access to memory than the Mainchannel over the same time interval thereby requiring less bandwidth.

For example, if one field line in a frame contains 16 pixels, the PIPchannel may only occupy 4 pixels of the total field in the frame whilethe Main channel may occupy the remaining 12 pixels. The amount of time,therefore, that the PIP channel has to access the memory to process 4pixels is four times longer than that of the Main channel and therebyrequires less bandwidth as shown by memory access timeline 1840 (i.e.,the PIP has a larger blank time interval). Therefore, in order to reducethe memory bandwidth that is required, the PIP channel may access thememory at a substantially slower rate and enable the Main channel to usethe remaining bandwidth.

BTO multiplexor 1650 may be configured to use various clock rates whenaccessing memory on different channels. For example, when a slower clockrate may be desired on a particular channel, BTO multiplexor 1650 mayreceive the requested data from the memory accessing block (client) 1820(i.e., PIP channel) using one clock rate 1844, store the data in a fieldline storage buffer, and access memory using a second clock rate (whichmay be slower) 1846. By preventing the client from using a high clockrate to access memory directly and instead using a field line buffer toaccess memory with a slower clock rate, the bandwidth requirement may bereduced.

BTO multiplexor 1650 may enable sharing of different channel field linebuffers which may further reduce the amount of storage required byoff-chip memory 300. This way BTO multiplexor 1650 may use the sharedfield line buffers to blend or overlay the different channels that sharea portion of the display.

The output of BTO multiplexor 1650 may be provided to color processingand channel blending video pipeline 560 (FIG. 5). FIG. 19 illustrates amore detailed description of the color processing and channel blending(CPCB) video pipeline 560. CPCB video pipeline 560 includes at least asampler 1910, a visual processing and sampling module 1920, an overlayengine 2000, and auxiliary channel overlay 1962, further primary andauxiliary channel scaling and processing modules 1970 and 1972, asignature accumulator 1990, and a downscaler 1980.

The functions of CPCB video pipeline 560 may include at least improvingvideo signal characteristics such as image enhancement by luma andchroma edge enhancement, and film grain generation and addition throughblue noise shaping mask. Additionally, the CPCB video pipeline 560 canblend at least two channels. The output of the blended channels may beselectively blended with a third channel to provide a three channelblended output and a two channel blended output.

As shown in FIG. 21, CMU 1930, which may be included in the overlayengine 2000 portion of the CPCB video pipeline 560, may improve at leastone video signal characteristic. The video signal characteristics mayinclude adaptive contrast enhancement 2120, brightness, contrast, hueand saturation adjustment globally in the image, intelligent remappingof color locally 2130, intelligent saturation control keeping the hueand brightness unchanged, gamma control through a look up table 2150 and2160, and color space conversion (CSC) 2110 to desired color space.

The architecture of CMU 1930 enables the CMU to receive video channelsignal 1942 in any format and convert the output 1932 to any otherformat. CSC 2110 in the front of the CMU pipeline may receive videochannel signal 1942 and may convert any possible 3-color space into avideo color processing space (e.g., converting RGB to YCbCr).Additionally, a CSC at the end of the CMU pipeline may convert from thecolor processing space into an output 3-color space. A global processingfunction 2140 may be used to adjust brightness, contrast, hue and/orsaturation and may be shared with the output CSC. Since CSC and globalprocessing function 2140 perform matrix multiplication operations, twomatrix multipliers may be combined into one. This type of sharing may beperformed by pre-computing the final coefficients after combining thetwo matrix multiplication operations.

CPCB video pipeline 560 may also provide dithering to a particularnumber of bits as may be required by a display device. An interlacer forthe at least one of the channel outputs may also be provided. CPCB videopipeline 560 may also generate control outputs (Hsync, Vsync, Field) forat least one of the channel outputs that may be displayed on a device.Also, CPCB video pipeline 560 may separate brightness, contrast, hue andsaturation adjustment globally for at least one of the output channelsand provide extra scaling and FRC for at least one of the outputchannels.

Referring again to FIGS. 16 and 19, channel outputs 1656, 1652, and 1654from FRC pipeline 550 are provided to CPCB video pipeline 560. Firstchannel 1656 may be processed along a first path which may use sampler1910 for up-sampling video signal on first channel 1656 and the output1912 of sampler 1910 may be provided to both a primary channel overlay1960 and an auxiliary channel over 1962 to produce a blended image forat least one of the outputs. Second channel 1652 may be processed alonga second path that provides visual processing and sampling on module1920. The output of the visual processing and sampling module 1920(which may up-sample the video signal) may be input to video overlay1940 (or overlay engine 2000) for blending or positioning a thirdchannel 1654 (which may also be run through sampler 1910) with theoutput. The function of overlay engine 2000 will be described in moredetail in connection with FIG. 20.

The output 1942 (which may be first video channel signal 1623 overlayedwith second video channel signal 1625) of video overlay may be providedthrough CMU 1930 to primary channel overlay 1960 and may also beprovided to a multiplexor 1950. In addition to receiving output 1942 ofvideo overlay, multiplexor 1950 may also receive outputs of visualprocessing and sampling module 1920 and sampler 1910. Multiplexor 1950operates to select which of its video signal inputs to provide toauxiliary channel overlay 1962. Alternatively, a multiplexor 1951 mayselect either the output of multiplexor 1950 or output 1932 of CMU 1930to provide as video signal output 1934 to auxiliary channel overlay1962. The arrangement of the processing units before the primary andauxiliary channel overlays enables the same video signal to be providedto the primary as well as the auxiliary channel overlays. After furtherprocessing by units 1970 and 1972, the same video signal (VI) may besimultaneously 1) output for display on primary output 1974 as a primaryoutput signal and 2) undergo further down-scaling prior to being outputfor display or storage on auxiliary output 1976 as auxiliary outputsignal.

In order to provide independent control of data selection to bothprimary output 1974 and auxiliary output 1976, the primary and auxiliarychannels may be formed by independently selecting first and second videochannel signals 1932 and 1934 from the first and second video channeloverlay module 1940. Auxiliary channel overlay module 1962 may selectthe first video channel signal 1652, the second video channel signal1654, or the overlaid first and second video channel signal 1942. SinceCMU 1930 is applied to first video channel signal 1652, second videochannel signal 1654 may be selected either before or after CMU 1930 bymultiplexor 1951 depending on whether the first and second video channelsignals have the same or different color spaces. Additionally, first andsecond video channel signals 1932 and 1934 may have independent blendingwith third video channel signal 1656.

CPCB video pipeline 560 may also provide scaling and FRC for auxiliaryoutput 1976 represented by downscaler 1980. This feature may benecessary in order to provide separate auxiliary output 1976 fromprimary output 1974. Since the higher frequency clock should be selectedas the scaling clock, the CPCB video pipeline 560 may run off theprimary output clock because the auxiliary clock frequency may be lessthan or equal to that of the primary clock. Downscaler 1980 may alsohave the capability of generating interlaced data, which may undergo FRCand output data formatting to be used as the auxiliary output.

In some scenarios, when the first channel is an SDTV video signal andprimary output 1974 should be an HDTV signal while auxiliary output 1976should be an SDTV video signal, CMU 1930 may convert the first channelSD video signal into HD video and then perform HD color processing. Inthis case, multiplexor 1950 may select as its output video signal 1942(signal that may not be passed through CMU 1930) thereby providing an HDsignal to primary channel overlay module 1960 and the processed SDTVsignal to auxiliary channel overlay 1962. Further auxiliary channelscaling and processing module 1972 may perform color control forauxiliary output 1976.

In some other scenarios, when the first channel is an HDTV video signaland primary output 1974 should be an HDTV signal while auxiliary output1976 should be an SDTV video signal, CMU 1930 may perform HD processingand multiplexor 1951 may select output of CMU 1932 to provide the HDTVprocessed signal to auxiliary channel overlay module 1962. Furtherauxiliary channel scaling and processing module 1972 may perform colorcontrol to change the color space into SDTV for auxiliary output 1976.

In some other scenarios, in which both primary and auxiliary outputs1974 and 1976 should be SD video signals, further channel scaling andprocessing modules 1970 and 1972 may perform similar color controlfunctions to place the signals in condition for output to correspondingprimary and auxiliary outputs 1974 and 1976.

It should be understood that if a video channel does not use aparticular portion of the pipeline in any of pipeline segments 540, 550,560, and 570 (FIG. 5) then that portion may be configured to be used byanother video channel to enhance video quality. For example, if secondvideo channel 1264 does not use de-interlacer 340 in FRC pipeline 550,then first video channel 1262 may be configured to use de-interlacer 340of second video channel pipeline in order to improve its video quality.As described in connection with FIG. 15, an additional noise reducer 330and an additional de-interlacer 340 may increase the quality of aparticular video signal by allowing shared memory pipeline segment 1260to process additional field lines simultaneously (e.g., 6 simultaneousfield line processing).

Some example output formats that may be provided using CPCB videopipeline 560 include National Television Systems Committee (NTSC) andPhase Alternating Line (PAL) primary and secondary outputs of the sameinput image, HD and SD (NTSC or PAL) primary and secondary outputs ofthe same input image, two different outputs in which a first channelimage is provided on the primary output and a second channel image isprovided on the auxiliary output, overlaid first and second channelvideo signals on the primary output and one channel video signal (firstchannel or a second channel) on the auxiliary output, different OSDblending factors (alpha values) on the primary and auxiliary outputs,independent brightness, contrast, hue, and saturation adjustments on theprimary and auxiliary outputs, different color spaces for the primaryand auxiliary outputs (e.g., Rec. 709 for primary output and Rec. 601for auxiliary output), and/or sharper/smoother image on an auxiliaryoutputs through the use of different sets of scaling coefficients on afirst channel scaler and a second channel scaler.

FIG. 20 illustrates in more detail overlay engine 2000 (FIG. 19).Overlay engine 2000 includes at least video overlay module 1940, CMU1930, first and second channel parameters 2020 and 2030, a selector2010, and a primary M-plane overlay module 2060. It should be understoodthat primary M-plane overlay 2060 is similar to primary channel overlay1960 (FIG. 19) but may include additional functionality that may be usedto blend or overlay further channel video signals 2040 with thirdchannel input 1912 (FIG. 19).

Overlay engine 2000 may generate a single video channel stream byplacing M available independent video/graphics planes on the finaldisplay canvas. In one particular embodiment overlay engine 2000 maygenerate a single channel stream by placing 6 planes on the finaldisplay canvas. Position for each plane on the display screen may beconfigurable. The priority of each plane may also be configurable. Forexample, if the position of the planes on the display canvas isoverlapped, then priority ranking may be used to resolve which plane isplaced on top and which plane may be hidden. The overlay may also beused to assign an optional border for each plane.

Examples of further video channel signals 2040 and their sources mayinclude a main plane which may be first channel video signal 1652, PIPplane which may be second channel video signal 1654, char OSD planewhich may be generated using an on-chip character OSD generator,bit-mapped OSD plane which may be generated using a bit-mapped OSDengine. The OSD images may be stored in a memory where a memoryinterface may be used to fetch various bit-mapped pre-stored objects inthe memory and place them on the canvas which may also be stored in thememory. The memory interface may also perform format conversions whilefetching the requested object. The bit-mapped OSD engine may read thestored canvas in a raster scan order and send it to the overlay.Additional video channel signals 2040 may include a cursor OSD planewhich may be generated by a cursor OSD engine and may use a smallon-chip memory to store the bit map of a small object like a cursor, anexternal OSD plane which is received from an external source. Theexternal OSD engine may send out the raster control signals and thedisplay clock. The external OSD source may use these control signals asa reference and send data in the scan order. This data may be routed tothe overlay. If an external OSD plane is enabled, Flexiport may be usedto receive the external OSD data.

Overlay 1940 before CMU 1930 may overlay first video channel stream 1653and second video channel stream 1655. Overlay 1940 may enable CMU 1930to perform more efficiently by allowing the CMU 1930 to operate on asingle video stream thereby obviating the need to replicate moduleswithin CMU 1930 for multiple video channel streams. Overlay 1940 inaddition to providing a single video channel signal 1942 to CMU 1930 mayalso provide a portion (i.e., pixel-by-pixel) indicator 1944 to CMU 1930that identifies the video portion as either belonging to the first videochannel stream or the second video channel stream.

Two sets of programmable parameters 2020 and 2030 that correspond tofirst video channel stream 1653 and second video channel stream 1655 maybe provided. Selector 2010 may use portion indicator 1944 to selectwhich programmable parameters to provide to CMU 1930. For example, ifportion indicator 1944 indicates that the portion processed by CMU 1930belongs to first video channel stream 1653, selector 2010 may provide toCMU 1930 programmable parameters 2020 that correspond to first videochannel stream 1653.

There may be the same number of layers as the number of video planes.Layer 0 may be the bottom most layer and the subsequent layers may havean increasing layer index. The layers may not have dimensional orpositional characteristics but instead may provide an order in whichthey should be stacked. Overlay engine 2000 may mix the layers beginningwith layer 0 and moving upwards. Layer 1 may be first blended with layer0 using a blend factor associated with the video plane put on layer 1.The output of layer 0 and layer 1 blending may then be blended withlayer 2. The blend factor that may be used may be the one associatedwith the plane put on layer 2. The output of the layer 0, layer 1, andlayer 2 blending may then be blended with layer 3 and so on until thefinal layer is mixed. It should be understood that one of ordinary skillmay choose to blend the layers in any combination without departing fromthe teachings of this invention. For example, layer 1 may be blendedwith layer 3 and then with layer 2.

It should also be understood that although overlay engine 2000 isdescribed in connection with the primary output channel, colorprocessing and channel blending pipeline 560 may be modified to providean M-plane overlay using overlay engine 2000 on auxiliary outputchannel.

FIG. 22 illustrates in more detail back end pipeline stage 570 of thevideo pipeline. Back end pipeline stage 570 may include at least aprimary output formatter 2280, a signature accumulator 1990, anauxiliary output formatter 2220 and a selector 2230.

Back end pipeline stage 570 may perform output formatting for bothprimary and auxiliary outputs and may generate control outputs (Hsync,Vsync, Field) as the auxiliary output. The back end pipeline stage 570may facilitate both digital and analog interfaces. Primary outputformatter 2280 may receive processed primary video channel signals 1974and generate a corresponding primary output signal 492 a. Auxiliaryoutput formatter 2220 may receive processed auxiliary video channelsignals 1976 and generate a corresponding auxiliary output signal 492 b.Signature accumulator 1990 may receive auxiliary video channel signals1976 and accumulate and compare the differences between the accumulatedsignals to determine the video signal quality of the output video signaland may provide this information to a processor to change systemparameters if necessary.

Auxiliary video channel signals 1976 may also be provided to a CCIR656encoder (not shown) prior to being formatted for output 492 b. TheCCIR656 encoder may perform any necessary encoding to place the signalin condition for external storage or some other suitable means.Alternatively auxiliary video channel signals 1976 may be provided asoutput signal 492 b without being encoded or formatted by using selector2230 to select bypass auxiliary video channel signal 2240.

An interlacing module (not shown) in back end pipeline stage 570 mayalso be provided. If an input signal is interlaced, it may first beconverted to progressive by de-interlacer 340 (FIG. 13). Thede-interlacer may be necessary because all the subsequent modules in thevideo pipeline stages may work in the progressive domain. The interlacerin back end pipeline stage 570 may be selectively turned on if aninterlaced output is desired.

The interlacer module may include at least a memory large enough tostore at least two lines of pixels but may be modified to store anentire frame if necessary. The progressive input may be written to thememory with the progressive timings. The interlaced timings in lock withthe progressive timings may be generated at half the pixel rate. Thedata may be read from the memory with the interlaced timings. Even fieldlines may be dropped in odd fields and odd field lines may be dropped ineven fields. This in turn may produce an interlaced output that issuitable for use with a given device.

Thus it is seen that apparatus and methods for providing multiplehigh-quality video channel streams using shared storage are provided. Aperson skilled in the art will appreciate that the present invention canbe practiced by other than the described embodiments, which arepresented for purposes of illustration rather than of limitation, andthe present invention is limited only by the claims which follow.

What is claimed is:
 1. A decoder for decoding a first input signalcomprising a first channel and a second channel, and a second inputsignal comprising a first channel and a second channel, the decodercomprising: a selection stage that: receives the input signals;selectively combines the first channel of the first input signal withthe first channel of the second input signal to provide a selectivelycombined signal; and selects the second channel of the first inputsignal and the second channel of the second input signal to provide twoselected channels; an analog to digital conversion stage that processesthe selectively combined signal and the two selected channels to providefour processed channels; and a decoder stage that receives the fourprocessed channels and outputs at least one decoded signal.
 2. Thedecoder of claim 1, further comprising a DC restore stage, wherein atleast one of the selectively combined signal and the two selectedchannels is passed through the DC restore stage prior to being processedby the analog to digital conversion stage.
 3. The decoder of claim 1,wherein the signal selection stage is configured to: time-divisionmultiplex the first channel of the first input signal and the firstchannel of the second input signal to provide the selectively combinedsignal.
 4. The decoder of claim 3, wherein: said time-divisionmultiplexing further comprises selecting the first channel of the firstinput signal during a first clock period of a first clock, and the firstchannel of the second input signal during a second clock period of thefirst clock; and said processing further comprises processing one of thetwo selected channels in accordance with the first clock, the other oneof the two selected channels in accordance with a second clock, and theselectively combined signal in accordance with the second clock and athird clock.
 5. The decoder of claim 4, wherein the first clock isapproximately inverse to the second clock.
 6. The decoder of claim 5,wherein the third clock is approximately twice as fast as the firstclock and the second clock.
 7. The decoder of claim 1, wherein theanalog to digital conversion stage comprises: a first analog to digitalconverter that performs analog to digital conversion on the selectivelycombined signal; a second analog to digital converter that performsanalog to digital conversion on one of the two selected channels; athird analog to digital converter that performs analog to digitalconversion on the other one of the two selected channels; and ademultiplexer that demultiplexes the converted selectively combinedsignal.
 8. The decoder of claim 1, wherein the decoder stage comprises:a first decoder, wherein the first decoder receives a first of the fourprocessed channels and a second of the four processed channels andoutputs the at least one decoded signal.
 9. The decoder of claim 8,wherein the decoder stage further comprises: a second decoder, whereinthe second decoder receives a third of the four processed channels and afourth of the four processed channels and outputs another decodedsignal.
 10. The decoder of claim 9, wherein the first decoder operatesin accordance with a first clock and the second decoder operates inaccordance with a second clock, wherein the first clock is approximatelyinverse to the second clock.
 11. A method for decoding a first inputsignal comprising a first channel and a second channel, and a secondinput signal comprising a first channel and a second channel, the methodcomprising: receiving the input signals; selectively combining the firstchannel of the first input signal with the first channel of the secondinput signal to provide a selectively combined signal; selecting thesecond channel of the first input signal and the second channel of thesecond input signal to provide two selected channels; performing ananalog to digital conversion to process the selectively combined signaland the two selected channels to provide four processed channels; anddecoding the four processed channels to produce at least one decodedsignal.
 12. The method of claim 11 further comprising restoring a DCcomponent of at least one of the selectively combined signal and the twoselected channels prior to performing said analog to digital conversion.13. The method of claim 11, wherein said selectively combiningcomprises: time-division multiplexing the first channel of the firstinput signal and the first channel of the second input signal to providethe selectively combined signal.
 14. The method of claim 13, wherein:said time-division multiplexing further comprises selecting the firstchannel of the first input signal during a first clock period of a firstclock, and the first channel of the second input signal during a secondclock period of the first clock; and said performing the analog todigital conversion further comprises processing one of the two selectedchannels in accordance with the first clock, processing the other one ofthe two selected channels in accordance with a second clock, andprocessing the selectively combined signal in accordance with the secondclock and a third clock.
 15. The method of claim 14, wherein thebeginning of a first clock period of the third clock is substantiallyaligned with the middle of a first clock period of the first clock. 16.The method of claim 13, wherein the first clock is approximately inverseto the second clock.
 17. The method of claim 16, wherein the third clockis approximately twice as fast as the first clock and the second clock.18. The method of claim 11, wherein the decoding further comprisesdecoding a first of the four processed channels and a second of the fourprocessed channels to produce the at least one decoded signal.
 19. Themethod of claim 18, wherein the decoding further comprises decoding athird of the four processed channels and a fourth of the four processedchannels to produce another decoded signal.
 20. The method of claim 19,wherein the decoding to produce the at least one decoded signal operatesin accordance with a first clock and the decoding to produce the otherdecoded signal operates in accordance with a second clock, wherein thefirst clock is approximately inverse to the second clock.